One of the most significant efforts in the design of electronic systems is the continuing effort to fit more and more active devices within a given area of a semiconductor substrate. This effort involves the reduction of the minimum geometries of semiconductor devices. Additionally, a reduction in the spacing between adjacent semiconductor devices also aids in increasing the density of the active surface area of a semiconductor substrate. If semiconductor devices are positioned too close to one another on a semiconductor substrate, parasitic capacitances and currents can develop which can degrade the performance of the circuit as a whole. As such, a great deal of effort has gone into designing methods and structures to electronically isolate adjacent semiconductor devices while still allowing the semiconductor devices to be positioned closely to one another.
One method of isolation that has been extensively applied in the past is the local oxidation of silicon (LOCOS) technique. Using the LOCOS technique and resulting LOCOS structures, the surface of the active semiconductor substrate is oxidized between active regions of the semiconductor surface to prevent the electronic interaction of adjacent devices. The effectiveness of the LOCOS technique degrades significantly as devices become closer and closer together due to parasitic currents that can develop between adjacent devices beneath the LOCOS structures. These currents are referred to as "punch-through" currents and travel through the bulk semiconductor beneath the LOCOS structures.
An additional method of isolation that has been used in the past is trench isolation. Using this technique, trenches are etched between adjacent active regions of the semiconductor substrate. Deep trenches are effective in preventing the punch-through currents described previously. However, the placement of trenches proximate semiconductor devices can create leakage problems within the devices themselves. For example, a trench that is used to isolate a field effect transistor can degrade the performance of the transistor by creating a conduction path across the channel of the transistor along the side wall of the trench. These current paths are due to the leakage along the surface of the trench side wall. Hence, while the trench can effectively eliminate the punch-through current between adjacent devices, the trench can degrade the performance of the device it is intended to isolate.
Accordingly, a need has arisen for an isolation structure and method that prevents the electronic interaction of adjacent active semiconductor devices but does not degrade the performance of the devices themselves.